In the fabrication of micro-mechanical components and electronic semiconductor devices in semiconductor wafers, a composite semiconductor wafer is formed. The composite wafer comprises a device layer in which the micro-mechanical components and/or the electronic semiconductor devices are to be formed and which is provided by a device layer forming wafer of semiconductor material, typically, silicon. The device layer is supported on a handle layer, which is formed by a separate handle layer forming wafer, also of semiconductor material, and typically, silicon. In general, the handle layer is a relatively thick layer formed from a wafer of thickness of 350 μm or greater, while the device layer is a relatively thin layer, and may be of thickness as thin as 1 μm, and in general, is seldom of thickness greater than 200 μm. More typically, the device layer is of thickness in the range of 3 μm to 50 μm. In general, the device layer is formed from a wafer of thickness of at least 350 μm, and more commonly of thickness of 500 μm, which is subsequently machined to the desired thickness in the range of 3 μm to 50 μm after formation of the composite wafer.
A buried layer, typically an oxide layer, in general, is located between the device layer and the handle layer. The oxide layer may be thermally grown or deposited, and may be formed on one or both of the device and handle layer forming wafers prior to bonding thereof. Where the oxide layer is formed on the handle layer forming wafer only, the device layer forming wafer is bonded to the oxide layer, and vice versa where the oxide layer is formed an the device layer forming wafer. Where the oxide layer is formed on both the handle and device layer forming wafers, the two oxide layers are bonded together. Bonding of the handle or device layer forming wafers to the oxide layer, or bonding of the two oxide layers together is typically carried out by high temperature fusion bonding in a high temperature anneal bonding process.
Silicon wafers, in general, are produced with one polished major surface, which comprises a peripheral ridge extending from the polished major surface. The ridge which results from the polishing process extends around the wafer adjacent the peripheral edge thereof. This peripheral ridge on the major surface of the device layer forming wafer, which when the composite wafer is formed faces the handle layer, in general, inhibits satisfactory bonding of the wafers around the peripheral edges thereof. This problem arises irrespective of whether a buried oxide layer or other buried layer is located between the two wafers or not. In general, adequate bonding is achieved between the wafers, or between the water and the buried layer, or between the burled layers, as the case may be, over the central area of the wafer and most of the areas of the major surface of the wafer towards the peripheral edge thereof. However, an annular band extends around the major surfaces of the wafers towards the peripheral edge thereof where bonding between the major surface of the wafer and the adjacent oxide layer or wafer is unsatisfactory. If the unbonded peripheral portion is left an the composite wafer, when the device layer forming wafer is machined to the appropriate thickness to form the device layer, the unbonded peripheral portion of the device layer tends to shatter and break off during transportation or subsequent processing, thus causing particle contamination of the wafer surface, the manufacturing line and other problems. Additionally, shattering of the device layer forming wafer adjacent the unbonded peripheral portion may also occur during mechanical polishing of the device layer forming wafer after the device layer forming wafer has been machined to the desired final thickness. Shattering of the unbonded peripheral portion of the device layer forming wafer during polishing leads to scratching of the polishing surface, which is undesirable.
In order to remove the unbonded peripheral portion of the device layer, a process which is commonly referred to as edge definition is carried out. This is carried out after the bonding of the two wafer together, or the bonding of the two wafer with the oxide layer located between the wafers. There are three commonly used methods for carrying out edge definition. One of the methods is a grinding method and the other two methods are commonly referred to as masking methods. In the grinding method the unbonded periphery of the device layer forming wafer is ground off using a suitable grinder. In one of the masking methods the unbonded periphery of the device layer forming wafer is etched. The etching of the unbonded periphery of the device layer forming wafer may be carried out before or after the device layer forming wafer has been machined to the desired finished thickness, and is carried out by appropriately masking and patterning the exposed major surface of the device layer forming wafer, and etching through the entire thickness of the device layer forming wafer. The etching is carried out by a wet silicon etch, such as, for example, a dilute hydrofluoric acid/nitric acid aqueous solution or a potassium hydroxide aqueous solution etch. The other masking method for carrying out edge definition is somewhat similar to the latter method, but requires dry etching of the unbonded periphery of the device layer forming wafer. In this method the exposed major surface of the device layer forming wafer is masked with a patterned photoresist layer, or a patterned photoresist layer with an oxide layer. The device layer forming wafer is then etched through its entire thickness to remove the unbonded periphery by a dry etch, such as an inductively coupled plasma etch (ICP etch) using sulphur hexafluoride as the etchant.
In general, these methods for removing the unbonded periphery of the device layer forming wafer are unsatisfactory, and suffer from a number of problems. Firstly, the grinding method whereby the unbonded periphery of the device layer forming wafer is ground from the composite wafer, depending on the grinding machine used, is often only suitable for semiconductor wafers where the total thickness of the handle and the device layer forming wafers prior to grinding to the thickness of the amount of material removed during grinding is more than two to one. Otherwise, the downward pressure on the composite wafer caused by the action of the grinding wheel of the grinder on the device layer forming wafer is sufficient to shatter the handle layer forming wafer adjacent the peripheral edge thereof. This, thus, prevents the use of this method for composite wafers having a relatively thick device layer and a relatively thin handle layer combination, in other words, a relatively thick silicon on oxide layer SOI and a handle layer which is relatively thin. Additionally, in this grinding method a subsequent chemical etch is required in order to remove crystal damage caused to the surface of the handle layer forming wafer around the peripheral edge of the composite wafer by the grinding, and the chemical etch attacks both the buried oxide layer and the back surface of the handle layer forming wafer, which is undesirable.
The masking methods require relatively expensive equipment for patterning the exposed major surface of the device layer forming wafer. Where the etch is a wet etch, the masking method causes under-etching of the buried oxide layer in composite wafers which comprise a buried oxide layer between the device and handle layer forming wafers. In composite wafers without a buried oxide layer where the device and handle layer forming wafers are bonded with a silicon/silicon bonded interface, the wet or dry etch causes a step to be formed in the handle layer around the peripheral edge thereof adjacent the silicon/silicon bonded interface. The step is formed in the handle layer due to the fact that the edge area of the composite wafer adjacent the bond interface is uneven, and cannot be masked, thereby leaving the edge area exposed to the etchant, which etches the step in the handle layer. In addition, the back surface of the handle layer must also be masked in order to prevent etching thereof by the etching solution.
The use of a dry etch with the masking method is unsuitable for relatively deep device layer forming wafers, due to attack by the etching gas on the underside and edges on the handle layer forming wafer. In addition, pinholes which may occur in the photoresist layer and/or a chemical vapour deposited masking layer result in pinholes being etched in the device layer forming wafer by the etching gas which penetrates through the pinholes in the photoresist and/or chemical vapour deposited masking layer. Indeed, the use of a dry etch with the masking method also causes a step to be formed in the handle layer forming wafer around the peripheral edge thereof adjacent the silicon/silicon bonded interface in composite wafers without a buried oxide layer.
There is therefore a need for a method for forming a composite semiconductor wafer which overcomes the problems of prior art methods.
The present invention is directed towards providing a method for forming a composite semiconductor wafer which overcomes the problems of prior art methods, and the invention is also directed towards providing a composite semiconductor wafer.